|Title||ANALYSIS OF VLSI INTERCONNECT DELAY PROBLEM FOR A CRITICAL PATH USING CAPACITIVE COUPLING|
Mayank Singh & Atul Verma
This paper gives an analysis of interconnect delay problem that exists in very large scale integration (VLSI) circuits. This problem of delay exist even when the interconnects are spaced close to each other but at a short distance. Capacitive coupling becomes significant in this scenario and it affects the capacitive cross-talk as well. Analysis has been done using same and opposite directions of aggressor switch. The paper also offers the different ways to improve the delay.